Gitweb: http://git.kernel.org/linus/31983a04d686f9f90b356072089d8d677e40e776
Commit: 31983a04d686f9f90b356072089d8d677e40e776
Parent: 4157d9f55435331deef01ba8a9a47f248c042fb2
Author: Mauro Carvalho Chehab <mchehab@redhat.com>
AuthorDate: Wed Aug 5 21:16:56 2009 -0300
Committer: Mauro Carvalho Chehab <mchehab@redhat.com>
CommitDate: Mon May 10 11:44:55 2010 -0300
Documentation/edac.txt: Add Nehalem specific EDAC characteristics
As Nehalem has a different binding to EDAC API, and its own different
error injection code, documents it.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
Documentation/edac.txt | 110 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 110 insertions(+), 0 deletions(-)
diff --git a/Documentation/edac.txt b/Documentation/edac.txt
index 79c5332..8bc3204 100644
--- a/Documentation/edac.txt
+++ b/Documentation/edac.txt
@@ -6,6 +6,8 @@ Written by Doug Thompson <dougthompson@xmission.com>
7 Dec 2005
17 Jul 2007 Updated
+(c) Mauro Carvalho Chehab <mchehab@redhat.com>
+05 Aug 2009 Nehalem interface
EDAC is maintained and written by:
@@ -717,3 +719,111 @@ unique drivers for their hardware systems.
The 'test_device_edac' sample driver is located at the
bluesmoke.sourceforge.net project site for EDAC.
+=======================================================================
+NEHALEM USAGE OF EDAC APIs
+
+This chapter documents some EXPERIMENTAL mappings for EDAC API to handle
+Nehalem EDAC driver. They will likely be changed on future versions
+of the driver.
+
+Due to the way Nehalem exports Memory Controller data, some adjustments
+were done at i7core_edac driver. This chapter will cover those differences
+
+1) On Nehalem, there are one Memory Controller per Quick Patch Interconnect
+ (QPI). At the driver, the term "socket" means one QPI. It should also be
+ associated with the CPU physical socket.
+
+ Each MC have 3 physical read channels, 3 physical ...
