> > If we really care about using the LAPIC timer on systems with deeper
If both cores goes into C1 at the same time, the chipset
can move the processor into a C3 like state called C1e.
For K7 and K8 through and including revision E, the LAPIC
timer is guaranteed to work in C1.
For K8 revisions F and G, and for upcoming family 0x10 and
0x11 parts, if either bit in MSRC001_0055[28:27] is set,
C1e is enabled and the LAPIC timer cannot be trusted in
AMD can craft a patch to sort this out as soon as we have
an idea what the framework is going to look like.
Operating Systems Research Center