On Sun, Jan 27, 2008 at 11:51:06AM +0200, Avi Kivity wrote:
quoted text
> Joerg Roedel wrote:
> >
> >> What happens to lazy fpu if we don't trap cr0 changes?
> >>
> >> Perhaps it's worth disabling lazy fpu with npt.
> >>     
> >
> > It should be implicitly disabled with npt because accesses to cr3 are
> > not intercepted anymore. The svm_set_cr3 function is the only place
> > which disables fpu switching.
> >   
> 
> Okay.  We may want to investigate enabling it later, but no hurry now.
> 
> On the other hand, we want to trap cr0 so the guest can't control the 
> cache disable bits.  Also cr4.pce and cr4.mce.

Is it a problem when the guest disables caching? It disables it only in
its own context because it has its own copy of cr0. Cr4.pce can be
accessible for the guests because there is no way for them to access the
performance counter MSRs. But I am not sure about MCE, I will check
that.
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