Olaf Kirch wrote:
quoted text
> Looks like the e1000 watchdog racing with some dhclient activity
> (upping the interface). 
 
quoted text
> I just noticed that the driver actually uses register pages. So it
> looks like it's possible to have something like this without the
> mutex: 
> 
> 	process A selects page A
> 	process B selects page B
> 	process A writes to register at offset A'

I think that is possible, which is why the mutex patch would be good for
the future.  However we have not shown that to be happening as a root
cause, but I don't rule it out.

so, why now?  Drivers since before the e1000/e1000e split had this same
code, with no reports of problems.  This code has been heavily tested,
and one of the platforms easily reproducing this has been available for
3 years now (ich8), with code that is basically unchanged in the driver.
 
quoted text
> So we may end up writing to the wrong register. I think I heard
> Vojtech mention 
> that the e1000e also has a register based interface to erase/rewrite
> the NVM programmatically. Do we know at which offsets these registers
> live? 

The flash control registers are documented in the ICH documentation, and
are located at physical memory location indicated by BAR1 in the config
space of device 0:19.0

I wonder if we couldn't put a check in to see if the value we end up
reading from the register controlling the operation matches the
operation we were expecting (read vs write vs block erase)
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