Is there an issue with anything _besides_ coherent DMA?
Could one have a special version of the accessors for drivers that want to
assume they are strictly ordered vs coherent DMA memory? That would be much
easier to get right, without slowing _everything_ down. The problem with the
raw versions is that on some arches they are much more raw than just not being
ordered w.r.t normal memory.
__raw_writel()
No ordering beyond what the arch provides natively. The only thing you can
assume is that reads and writes to the same location on the same CPU are
ordered.
writel()
Strictly ordered with respect to any other IO, but not to normal memory.
(this is what Documentation/memory-barriers.txt claims). Should probably be
strictly ordered vs locks as well. Would be strictly ordered w.r.t. the
streaming DMA sync calls of course.
strict_writel()
Strictly ordered with respect to normal (incl. coherent DMA) memory as well.
One could even go as far as to allow a driver to "#define WANT_STRICT_IO" and
then it would get the strict versions. Add that to any driver that uses DMA
and then worry about vetting those drivers.
It's also worth nothing that adding barriers to IO accessors doesn't mean you
never have to worry about barriers with coherent DMA. Inherent with coherent
DMA, and driving hardware in general, there are various sequence points where
one must be sure one operation has finished before starting the next. Making
sure you're doing with DMA memory before telling the hardware to do something
with it a common example. Often the "telling the hardware to do something" is
done via an IO accessor function, but not always.
You can have buffer descriptors in DMA memory that describe the DMA buffers to
the hardware. It would be critical to be finished reading a DMA buffer before
updating the descriptor to indicate that it's empty. You could trigger a DMA
operation not by a call to an IO accessor, but with an atomic operation to a
variable shared with an ISR. When the ISR runs it sees the change and does
the necessary IO.
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