RE: [PATCH 01/01][retry 5] x86: L3 cache index disable for 2.6.26

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To: Ingo Molnar <mingo@...>
Cc: Greg KH <greg@...>, Pavel Machek <pavel@...>, Deguara, Joachim <joachim.deguara@...>, <gregkh@...>, <tglx@...>, <mingo@...>, <hpa@...>, <linux-kernel@...>
Date: Friday, August 15, 2008 - 4:02 pm

> > >  Author: Mark Langsdorf <mark.langsdorf@amd.com>

Yes.  Single inline function with asm instructions and 
a documented clflush check in asm/processor.h and the 
call to wbinvd_halt() in both processor_32.c and 
processor_64.h.  It looks like we're done here.

-Mark Langsdorf
Operating System Research Center
AMD

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Messages in current thread:
[PATCH 01/01] x86: L3 cache index disable for 2.6.26, Mark Langsdorf, (Fri Jul 18, 5:03 pm)
RE: [PATCH 01/01][retry 5] x86: L3 cache index disable for 2..., Langsdorf, Mark, (Fri Aug 15, 4:02 pm)
Re: [PATCH 01/01] x86: L3 cache index disable for 2.6.26, Mark Langsdorf, (Tue Jul 22, 2:06 pm)
RE: [PATCH 01/01] x86: L3 cache index disable for 2.6.26, Langsdorf, Mark, (Mon Jul 28, 10:54 am)