Re: [PATCH -v4 1/2] lib, Make gen_pool memory allocator lockless

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From: Andrew Morton
Date: Tuesday, November 16, 2010 - 2:50 pm

On Tue, 16 Nov 2010 08:53:10 +0800
Huang Ying <ying.huang@intel.com> wrote:


The code assumes that cmpxchg is atomic wrt NMI.  That would be news to
me - at present an architecture can legitimately implement cmpxchg()
with, say, spin_lock_irqsave() on a hashed spinlock.  I don't know
whether any architectures _do_ do anything like that.  If so then
that's a problem.  If not, it's an additional requirement on future
architecture ports.


That sentence needs a fixup.


These are waaaay too big to be inlined.  Let the compiler decide.

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Messages in current thread:
[PATCH -v4 0/2] Lockless memory allocator and list, Huang Ying, (Mon Nov 15, 5:53 pm)
Re: [PATCH -v4 0/2] Lockless memory allocator and list, Peter Zijlstra, (Tue Nov 16, 4:49 am)
Re: [PATCH -v4 0/2] Lockless memory allocator and list, Linus Torvalds, (Tue Nov 16, 9:38 am)
Re: [PATCH -v4 0/2] Lockless memory allocator and list, Peter Zijlstra, (Tue Nov 16, 11:04 am)
Re: [PATCH -v4 1/2] lib, Make gen_pool memory allocator lo ..., Andrew Morton, (Tue Nov 16, 2:50 pm)