Looking through code following up on the separate TSC-related
thread, I noticed that my Intel Core 2 Duo "Conroe" box
is determined to have an unstable TSC, so falls back
While a Conroe has X86_FEATURE_CONSTANT_TSC and not
X86_FEATURE_NONSTOP_TSC, a Conroe is only able to enter
C0 and C1 (unlike its sister Intel Core 2 Duo processor
"Merom" which can enter C0-C3).
I was under the impression (possibly from an earlier kernel
version?) that tsc_constant PLUS inability to enter deep-C
states would result in an acceptably stable TSC to use
as a clocksource (assuming it passes a TSC warp test).
So is this a bug? Or is my impression incorrect?
See tsc_check_state() in drivers/acpi/processor_idle.c.
I can submit a patch, but wanted to check first.
On Wed, May 26, 2010 at 10:41 AM, Dan Magenheimer
tsc_check_state(0 should only mark TSC unstable when state > C1 and
!NONSTOP_TSC. Are you seeing TSC marked even with only C1?
Or may be you are hitting the bug in acpi_pad.c that marks TSC
unstable more aggressively. I recently sent out a patch for that here