* Darrick J. Wong <djwong@us.ibm.com> wrote:

quoted text
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
> 
> Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> 
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index fb99f7e..967c646 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -103,11 +103,14 @@ int use_calgary __read_mostly = 0;
>  #define PMR_SOFTSTOPFAULT	0x40000000
>  #define PMR_HARDSTOP		0x20000000
>  
> -#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS		8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> -#define PHBS_PER_CALGARY	4
> +/*
> + * The maximum PHB bus number.
> + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> + * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> + */
> +#define MAX_PHB_BUS_NUM		384

Doesnt build:

arch/x86/kernel/pci-calgary_64.c: In function ?calgary_locate_bbars?:
arch/x86/kernel/pci-calgary_64.c:1107: error: ?PHBS_PER_CALGARY? undeclared (first use in this function)
arch/x86/kernel/pci-calgary_64.c:1107: error: (Each undeclared identifier is reported only once
arch/x86/kernel/pci-calgary_64.c:1107: error: for each function it appears in.)

i have added back the PHBS_PER_CALGARY line - that is still needed, right?

Thanks,

	Ingo
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